1. Field of the Invention
The present invention relates to a semiconductor memory device and more particularly to a boosting circuit for boosting an internal voltage.
2. Description of the Related Art
Generally, a semiconductor memory device such as dynamic random access memory (DRAM) functions to move an effective potential. The potential in a DRAM constructed using CMOS transistor technology experiences a voltage drop of somewhat more than a threshold voltage of a MOS transistor in the process of being transmitted through the channel region of the MOS transistor. Such voltage drops potentially cause information losses as well as acting as inhibiting accurately performing data reading and writing operations.
The continuing increases in the density and capacity of semiconductor memory devices have caused a commensurate increase of power consumption. For this reason, the semiconductor memory devices use an internal voltage source to lower the power consumption and to enhance the reliability of operation thereof.
In order to correctly read/write data from/to a memory cell composed of a MOS transistor and a capacitor, a voltage sufficient to overcome the threshold voltage of the MOS transistor should be provided. Thus, for example, a voltage boosted by 1.5 V compared to the internal voltage is typically provided to the word line that becomes the gate of the MOS transistor.
FIG. 1 is a diagram showing an internal voltage boosting circuit according to a prior art. The internal voltage boosting circuit of FIG. 1 includes an oscillator 8 for outputting an output signal of internal voltage IVC level, pumping capacitors 2 and 4 receiving the output of the oscillator 8 at their one ends and pumping nodes A and B respectively connected to their other ends. and a transmission transistor 6 having its drain connected to the pumping node A, its gate connected to the pumping node B and its source outputting a boosted voltage VPP. A precharging circuit (not shown) for precharging the pumping nodes A and B to a predefined voltage level is also included in the circuitry
In operation, upon power-up of a chip or the beginning of an active cycle, the oscillator 8 starts to oscillate whenever the boosted voltage VPP falls below a prescribed voltage level. The pumping capacitors 2 and 4 are thus pumped by the output of IVC level output from the oscillator 8. The voltage that the pumping node A is charged to is applied via the channel of the transmission transistor 6 as the boosted voltage VPP. However, when using a lower internal voltage in an effort to reduce power consumption as has become the recent trend, it is impossible to raise the boosted voltage VPP to the desired voltage level. The reason is that even after precharging the pumping nodes A and B by a predetermined voltage and then pumping the voltage, the pumping nodes A and B cannot be boosted enough due to the lower pumping voltage and the fact that the boosted voltage VPP is reduced by the threshold voltage of the transmission transistor 6.
Specifically, when the pumping nodes A and B are precharged by the internal voltage IVC and pumped by the IVC level output from oscillator 8, the pumping nodes A and B are raised to a 2IVC level. The boosted voltage VPP will then be 2IVC-Vth (wherein Vth represents a threshold voltage of the transmission transistor 6). However, though the boosted voltage VPP level increases, there also occurs a voltage drop greater than the threshold voltage Vth due to the body effect (also called substrate bias effect) of the transmission transistor 6. If a low internal voltage IVC is used to avoid such a voltage drop, it is difficult for the boosted voltage VPP to reach the desired boosted voltage level of IVC+1.5 V and, even if it does, stable operation of the chip can not be ensured due to the deterioration of the driving capability.
When the pumping nodes A and B are precharged by a power supply voltage VCC and then pumped by the output of IVC level from the oscillator 8 the above mentioned difficulty appears. For example, assuming that the external voltage is 2.8 V, the internal voltage IVC is 2 V, and the pumping efficiency is 100%, the pumping nodes A and B will be boosted to 4.8 V. However, although the boosted voltage VPP should be above 3.5 V as described above (2.0+1.5), the gate-source voltage Vgs of the transmission transistor 6 falls below 1.3 V. Thus, even though the transistor 6 is turned on, it is impossible to obtain a stable boosted voltage VPP due to the reduction of the driving capability thereof.
The boosting circuit having the construction as shown in FIG. 1 is fabricated in accordance with a typical CMOS manufacturing process. Thus, an NMOS transistor fabricated this the CMOS manufacturing process is used for the transmission transistor 6. Due to this construction, the circuit of FIG. 1 has a pumping efficiency problem, since it is well known in the art that an increase in the voltage level applied to the source and drain of the MOS transistor causes an increase in the body effect thereof. Further still, the increase in the density of semiconductor memory devices results in the miniaturization of circuit elements and results in smaller intervals between circuit elements, which further exacerbates the body effect problem. Accordingly, the boosting circuit of FIG. 1 has a problem of low pumping efficiency. In addition, even though it is possible to obtain the boosted voltage of desired level, the reliability of the chip operation can not be ensured due to the deterioration of driving capability of the transmission transistor.